Presentation Schedule

All times EST.
Welcome / Morning Session
Olof Kindgren
SERV : The World’s Smallest RISC-V (AMA)
Anne Elster
The European Factor: Europe´s Impact on Computing & Processors
Xi Wang, Brody Williams and Nathan Stoddard
xBGAS: Extended Base Global Address Space for High Performance Computing [Presentation]
Theodore Omtzigt and Peter Marosan
Introducing the Cambridge Architecture [Presentation]
Pantea Kiaei, Yuan Yao and Patrick Schaumont
Real-time Detection and Adaptive Mitigation of Power-based Side-Channel Leakage in SoC [Paper]
Xinfei Guo
Cross-layer Codesign for Resilient Hardware [Presentation] [Paper]
Ron Minnich
Building small stateless network-controlled appliances with linuxboot and Plan 9's cpu command [Presentation]
Lunch/ Discussion
Udit Gupta, Young Geun Kim, Sylvia Lee, Jordan Tse, Hsien-Hsin S. Lee, Gu-Yeon Wei, David Brooks and Carole-Jean Wu
Illuminating the Elusive Carbon Footprint of Computing [Paper]
Connor Kenyon, Glenn Volkema and Gaurav Khanna
Overcoming Limitations of GPGPU-Computing in Scientific Applications [Paper]
Casey Nelson, R. Iris Bahar and Tamara Lehman
Investigating the Potential for Near Data Processing to Reduce Secure Memory Overheads [Presentation] [Paper]
Trinayan Baruah, Yifan Sun, Ali Tolga Dincer, Saiful A Mojumder, José L Abellán, Yash Ukidave, Ajay Joshi, Norman Rubin, John Kim and David Kaeli
Griffin: Hardware-Software Support for Efficient Page Migration in Multi-GPU Systems
Samuel Hsia, Mark Wilkening, Udit Gupta, Caroline Trippel, Carole-Jean Wu, David Brooks and Gu-Yeon Wei
Cross-Stack Characterization and Solid State Drive-Based Near Data Processing for Recommendation Workloads [Presentation] [Paper] [arXiv]
Samuel Thomas, Tamara Lehman, R. Iris Bahar and Joseph Izraelevitz
Partial Recovery of Secure Non-Volatile Main Memories [Presentation]
Steven Hoover
Tutorial: Transaction-Level Verilog and its Ecosystem [Presentation] [Video]
Rob Landley, D. Jeff Dionne
Why the J-core Open Processor is Cool (AMA) [Presentation] [Video]


Registration is not required this year.

Call for Abstracts


The goal of BARC is to provide a forum for computer architects in the Greater Boston area and beyond to get together and present/discuss the 'latest and greatest' in the area of computer architecture. Papers are being sought on many aspects of computer architecture, including (but not limited to):

  • Microarchitecture
  • Multicore/manycore processors
  • GPUs
  • Memory systems
  • I/O
  • Networking and communication
  • Low power
  • Adaptive and hybrid systems
  • Architectures based on emerging technologies
  • Accelerator-based architectures
  • Embedded processing
  • Performance evaluation techniques
  • Important Dates:

    Deadline Extended January 15, 2021
    Abstract Submission Deadline: January 22, 2021
    Author Notification: January 23, 2021
    Workshop Date: Friday, January 29, 2021


    We invite abstracts, two pages or shorter, for consideration for presentation at BARC 2021. We will also have a session of lightning talks - you should denote a lightning round talk in your title as "Lightning Round". Authors may present work they have already published elsewhere, or plan to publish in the future. We welcome participation from those outside of the Greater Boston area.

    Please submit your abstract (in PDF format) using EasyChair:

    Abstracts will be accepted for a Zoom presentation or a YouTube with live chat option.

    For questions, contact Kurt Keville or Josh Gyllinsky.

    The final manuscripts of all accepted abstracts will be posted on the BBARC 2021 website. Please use the following guidelines for preparing the final manuscript: The technical program of BARC 2018 includes both oral presentations and poster presentations. Each oral presentation will be 20 minutes long (including Q&A). Poster authors should print their posters and bring to the workshop. The size of the posters can be up to 8'x4'.


    BARC 2021 will be held virtually. Login info TBD.