BARC 2020, Januray 31, 2020, Final Schedule

Program Schedule (Full talks are 20 minutes - lightning talks are 5 minutes).

8:30–8:35
Welcome - Srinivas Tadigadapa, Chair, ECE Dept., Northeastern
8:45–9: 15
Keynote - “RISC-V: Paving the Path for ISA Revolution” Shubu Mukherjee, Chief SoC Architect, SiFive.
9:15–10:15
Neural Network Acceleration - (3 papers)
1.
RecNMP: Accelerating Personalized Recommendation with Near-Memory Processing
L. Ke, U. Gupta, C.-J. Wu, B. Cho, M. Hempstead, B. Reagan, X. Zhang, D. Brooks, V. Chandra, U. Diril, A. Firoozshahian, B. Jia, K. Hazelwood, H.-H. Sean Lee, M. Li, B. Maher, D. Mudigere, M. Naumov, M. Schatz, M. Smelyanskiy and X. Wang, Washington U. St. Louis, Harvard U., Facebook, U. of Texas and Tufts U
2.
A Desirable Sparsity Dimension for Real-time Acceleration
X. Ma, F.-M. Guo, W. Niu, B. Ren and Y. Wang, Northeastern University and College of William and Mary
3.
An End-to-end RISC-V Solution for ML on the Edge Using In-pipeline Support
Z. Azad, M. S. Louis, L. Delshadtehrani, A. Ducimo, S. Gupta, P. Warden, V. J. Reddi and A. Joshi, Boston U., Google and Harvard U
10:15–10:30
Break
10:30–11:30
Security and Speculation - (3 papers)
4.
SCC: Compiling Sequential Code for Effective Speculative Parallelization in Hardware
V. Ying, M. Jeffrey and D. Sanchez, MIT and U. of Toronto
5.
Prefetching, Pre-Execution and Branch Outcome Streaming for In- Memory Database Lookups
M. Cavus, M. Shatnawi, R. Sendag and A. Uht, U. of Rhode Island
6.
A Programmable Hardware Monitor for Security of RISC-V Processors
L. Delshadtehrani, S. Canakci, B. Zhou, D. Eldridge, A. Joshi and M. Egele, Boston University and IBM
11:30–12:10
Lightning Round 1 - (7 papers)
7.
PERQ: Fair and Efficient Power Management of Power-Constrained Large-Scale Computing Systems
T. Patel and D. Tiwari, Northeastern University
8.
BlackParrot: An Open-Source RISC-V Multicore Processor A core for and by the world!
Z. Azad, S. Canakci, S. Davidson, P. Gao, F. Gilani, T. Guarino, T. Jung, D. Petrisko, B. Veluri, M. Wyse, C. Zhao, M. Oskin, M. Bedford Taylor and A. Joshi, Boston U. and U. of Washington
9.
Accelergy: An Architecture-Level Energy Estimation Methodology for Accelerator Designs
Y. Wu, J. Emer and V. Sze, MIT and NVIDIA
10.
Adaptive Low-Power Sensing and Activity Recognition for Wearable Devices
M. Neseem, J. Nelson and S. Reda, Brown U
11.
A Privacy-Preserving-Oriented DNN Pruning and Mobile Acceleration Framework
Z. Zhan, Y. Gong, Z. Li, W. Niu, X. Ma, B. Ren, C. Ding, X. Lin and Y. Wang, Northeastern U., College of William and Mary, and U. of Connecticut
12.
Mutual Information Accelerator for Autonomous Robot Exploration
P. Li, S. Karaman and V. Sze, MIT
13.
VFS-based Fault Injections on GPUs
M. Sabbagh, Y. Fei and D. Kaeli, Northeastern U
12:10–1:30
Lunch
1:30–2:30
Potpourri - (3 papers)
14.
MaxNVM: Maximizing DNN Storage Density and Inference Efficiency with Sparse Encoding and Error Mitigation
L. Pentecost, M. Donato, B. Reagen, U. Gupta, S. Ma, G.-Y. Wei and D. Brooks, Harvard U. and New York U
15.
IgnoreTM: Opportunistically Ignoring Timing Violations for Energy Savings using HTM
A. Alkhatatbih, M. Malekzadeh, T. Moreshet, I. Bahar and D. Papagiannopoulou, UMass Lowell, Boston U. and Brown U
16.
Accelerating Transformers-based Large-Scale Language Representation using FPGA
S. Zhou, B. Li and C. Ding, U. of Connecticut
2:30–2:45
Break
2:45–3:45
Lightning Round 2 - (9 papers)
17.
Daisen: A Visualization Framework for Computer Architecture Simulation
Y. Sun, Y. Zhang, A. Mosallaei and D. Kaeli, Northeastern U
18.
Thermo-GC: Reducing Write Amplification by Tagging Migrated Pages during Garbage Collection
S. Pei, J. Yang and Q. Yang, U. of Rhode Island
19.
Characterizing and Optimizing Systems for Neural Recommendation
U. Gupta, S. Hsia, V. Saraph, X. Wang, B. Reagan, K. Hazelwood, G.-Y. Wei, H.-H. Lee, D. Brooks and C.-J. Wu, Harvard U. and Facebook
20.
Preventing Cache-Based Side-Channel Attacks with Obfuscating Cache Architectures
E. del Rosario, L. MA and M. Kinsy, Boston U
21.
Attacking Memory-Hard Scrypt with Near-Data-Processing
J. Choe, T. Moreshet, I. Bahar and M. Herlihy, Brown U. and Boston U
22.
Software-Hardware Co-design of Generative Inference for Robust Robot Manipulation
Y. Liu and R. Bahar, Brown U
23.
Extending Hardware TCB Beyond CPU Chips
Z. Xu, T. Mauldin, Z. Yao, T. Wei, S. Pei and Q. Yang, U. of Rhode Island
24.
Retrieving Weights and Biases of Multi-layer Perceptrons
C. Gongye, Y. Fei and T. Wahl, Northeastern U
25.
CSB-RNN: A Super Real-time RNN Framework with Compressed Structured Block
R. Shi, P. Dong, T. Geng, M. Herbordt, H. So and Y. Wang, U. of Hong Kong, Northeastern U. and Boston U
3:45
Closing

Program Committees

David Kaeli - Northeastern University - chair

Yanzhi Wang - Northeastern University - chair

Caiwen Ding - Northeastern University - PC member

Ayse Coskun - Boston University - PC member

Vijay Janapa Reddi - Harvard University - PC member

Resit Sendag - University of Rhode Island - PC member

Devesh Tiwari - Northeastern University - PC member

Augustus Uht - University of Rhode Island - PC member

Carole-Jean Wu - Facebook - PC member

Sherief Reda - - Brown University - PC member

Yunsi Fei - Northeastern University - PC member

Mark Hempstead - Tufts University - PC member

Martin Herbordt - Boston University - PC member

Xue Lin - Northeastern University - PC member

Daniel Holcomb - UMass Amherst - PC member

Ajay Joshi - Boston University - PC member

Michel Kinsey - Boston University - PC member 

John Emer - MIT - PC member

Registration

The registration is now open. Link here.

Registration includes breakfast, light lunch, and coffee during all breaks.

Students have to provide the name of their advisor (this is to limit random people from showing up).

Call for Papers

Scope:

The goal of BARC is to provide a forum for computer architects in the Greater Boston area and beyond to get together and present/discuss the “latest and greatest” in the area of computer architecture. Papers are being sought on all aspects of computer architecture, including (but not limited to):

  • Microarchitecture
  • Multicore/manycore processors
  • GPUs
  • Memory systems
  • I/O
  • Networking and communication
  • Low power
  • Adaptive and hybrid systems
  • Architectures based on emerging technologies
  • Accelerator-based architectures
  • Embedded processing
  • Performance evaluation techniques

    • Important Dates:

    Submission Deadline: January 20, 2020
    Author Notification: January 25, 2020
    Workshop Date: Friday, January 31, 2020

    Submissions:

    All submissions must be made electronically through the EasyChair system. We invite 1-2 page abstracts for consideration for presentation at BARC 2020. We will also have a session of lightening talks - you should denote a lightening round talk in your title as Lightening Round: Paper Title. Authors may present work they have already published elsewhere, or plan to publish in the future. We welcome participation from those outside of the Greater Boston area.

    Please submit your abstract (in PDF format) using EasyChair:
    https://easychair.org/conferences/?conf=barc2020.

    For questions, contact Yanzhi Wang or David Kaeli.

    The final manuscripts of all accepted abstracts will be posted on the BARC 2019 website. Please use the following guidelines for preparing the final manuscript: The technical program of BARC 2019 includes both oral presentations and poster presentations. Each oral presentation will be 20 minutes long (including Q&A). Poster authors should print their posters and bring to the workshop. The size of the posters can be up to 8'x4'.

    Directions

    BARC 2020 will be held at the Raytheon Ampitheater in Egan Research Center, in Northeastern University. The full address is 120 Forsyth St, Boston, MA 02115.

    If you need parking: https://www.northeastern.edu/eventvenues/directions-parking/.